--- Quote Start ---
create_clock -period 10 -name my_clk [get_ports clk]
set_input_delay -max 3 -clock my_clk [get_ports ina]
set_ouput_delay -max 3 -clock my_clk [get_ports outa]
set_max_delay 2 -from ina -to outb
When Quartus tools analysis the 3rd timing path, the required time calculated as follows:
3(input_delay) + 3(output_delay) + 2(max_delay) + tdelay(com logic delay) <10(clock cycle)
But I want to constraint the delay less than 2ns from ‘ina’ to ‘outb’,
--- Quote End ---
You're already constraining that.
You're giving TimeQuest two sets of constraints
- tdelay < 2.0 from the set_max_delay constraint.
- 3 + tdelay + 3 < 10, from the set_input_delay and set_output_delay constraints.
That said, achieving a 2.0 ns delay is going to be hard, if not impossible.
Honored Contributor
