Forum Discussion
Occasional ContributorAbout the minimum value constraint (-min option) of "set output delay"
Hello,
You can find set_output_delay documentation here: https://www.intel.com/content/www/us/en/docs/programmable/683243/23-1/output-constraints-set-output-delay.html
Yes, fitter is notified of the setup and hold timing requirements from the set_output_delay. So fitter will do its best to meet this requirement during place & route.
Regards,
Nurina
Super ContributorFor all of this, check out this training: https://cdrdv2.intel.com/v1/dl/getContent/652837?explicitVersion=true
1) Yes, this is correct. Discussed in the training and the Timing Analyzer user guide found here: https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/user-guides.html
2) The calculated value here is just for the constraint to basically tell the Fitter how early the signal can be launched from the FPGA and still remain active and stable long enough to meet hold timing. Are you asking about the actual slack on the path to the external (downstream) device? If the slack is positive, then it meets hold timing. If it's negative, it fails. The value you enter into the constraint is not slack.
3) Again, the value here is not slack. There's no reason why the output delay min value can't be negative but you still get positive slack for the path.
Yamada1Thank you for answering.
Delay on board=1ns
Clock skew on board = -1ns
Hold time of subsequent device=3ns
In the above conditions, the setting value of "set output delay -min" can be calculated as 1-(-1)-3=-1ns. If this is set as a setting value of "set output delay -clock[clk] -min -1 [get ports DATA]", then "DATA delay from the clk edge must be 1 ns or more to satisfy the hold time". Is it correct to understand that the Fitter is notified of this?
I'm sorry to trouble you, but it would be helpful if you could teach me.
