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Altera_Forum
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16 years ago

about LVDS word alignment

Hello, I'm now using an A/D with serial LVDS output, it's 8-bit a word, and offers a DCO and a FCO, which is bit-sync signal and frame-sync signal, respectively. The frequency of DCO is half the data rate of input data, and the frequency of FCO is the same as sample rate, with positive edge at MSB of input data.

The quenstion is how should I do to get word alignment using rx_channel_data_align signal in ALTLVDS Receiver IP? I tested several times, and I can be sure that it's aligned when clockout of ALTLVDS Receiver is just opposite to FCO. How can I know how many pulses rx_channel_data_align signal gives when it's just aligned? Should I use extra logic cells and use a clock of double frequency of DCO?

Thank you!

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    try this:

    pass data as usual, also pass FCO through serdes with same serilisation factor. you will get patterns like 00100000 then pulse the alignment until you get 10000000
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Great! It seems so simple, why didn't I think it out! Thanks a lot!

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    are you sure that the output, when aligned, should not be 11110000 instead of 10000000 when feeding ALTLVDS it frame sync signal?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yes,I am sure.

    each data byte is serial 8 bits xxxx xxxx (x = 0 or 1)

    the sync signal is treated as byte of 00001000 00001000...etc. so only one bit should be high as long it a sync for one bit e.g. MSB or LSB as per protocol
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yeah, that's right! The patterns should be in fact "00001111" or "11110000", something like that, for DCO is of 50% duty.

    I think Kaz gave a perfect ideal, although the pattern given was incorrect.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    kaz, you call it a "sync signal". You can choose that to be anything you want? Then a series of 0's and only one 1 is good choice.

    If you were to use the frame sync input clock as your data stream to align your data word, you need to get output 11110000.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi,

    I am doing similar design here i.e. using ADC with serial LVDS output and pass it to altlvds rx for deserialization. I am stuck at the data alignment part. My ADC does give an output of FRAME signal, but how can I pass this signal to altlvds rx for comparison with the parallel output data from altlvds rx to determine if word alignment is achieved? Is the any sample of user logic for doing the comparison that can be shared? Thanks.