Honored ContributorIn Verilog, we have two types "and", logic and "&&" and bitwise and "&". In the following case:
wire [1:0] a; wire b; wire c; assign c = (a==2'b01) && (b==1'b1); assign c = (a==2'b01) & (b); Will I get the same result for wire "c"? For the statement "a==2'b01", can we think the return value of it be same as a value of wire or reg? If it is, I think the result of "c" is same. Thanks in advance.
Honored ContributorYes, the result of the two assign statements are the same. A couple of things you need to watch out for in more complex expressions.
The precedence of the bitwise and &, and the bitwise or | operators are both higher than both the logical operators && and ||. This gets very confusing when you mix these operators in the same expression. I tend to only use the logical operators unless you really need the bitwise functionality - it is a clearer description of your design intent. You could also have written assign c = a==2'b02 && b; Another issue for non-synthesizable code is that the && and || operators may use short-circuit evaluation. That means if you have expression a && functioncall(b) the functioncall may not get called if a is 0.
