About Floating Point Performance and New Accelerator Cards

Hi everyone,

I read the TDFIR Optimization Guide provided with the TDFIR opencl example, which mentioned the performance of floating point functions to be arround 500~300Mhz depends on type of operation. But it also mentioned that some ALUTs are required to implement each floating point function. Since the FPGA itself only runs at 2xxMhz speed, does that mean the floating point operations are all capped at 2xxMhz? Also, for Add/Sub operations the guide did not list usage of 27x27 Multipliers. Does that means for Stratix V, floating point Add/Sub can only be implemented by "soft" logic, not the DSP?

In addition, I am just wondering if anybody know what is the typical power usage of a Arria 10 OpenCL accelerator card? Is it similar to the Stratix V A7 (~25W) or Stratix V D8 (~75W) or something in between?

Thanks!

Ryan