About edge aligned souce synchronous interface

It depends what the other device is doing. Let's say it's feeding another FPGA that phase-shifts the clock 90 degrees. In that case, everything works out fine. You're right that somebody needs to shift the clock into the middle of the data eye, it just doesn't have to be the device you're constraining. (Rather than doing edge-aligned, I usually say that the other device is doing the phase-shift by putting a "-phase 90" on the create_generated_clock applied to the output port sending the clock off chip. This does nothing directly to the clock, it just says the external receiver is shifting it).