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Altera_Forum
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14 years ago

about clock-as-data analysis

Hi,

I am checking clock-as-data analysis descriptions in the 《qts_qii53018 - The Quartus II TimeQuest Timing Analyzer》and then so confused about figure 6-14 and its related descriptions:

"In this figure, the inverter feedback path is analyzed during timing analysis. The output of the divider register is used to determine the launch time and the clock port of the register is used to determine the latch time."

I think that both launch edge and latch edge should have been from the clock port of the divider register, which however actually conflicts with above.

for your convenience, i post related sections here as attached. anybody can explain more details?

looking forward to your help. thanks.

BR,

Fisher Cheng

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    For the clock divider, they didn't explicitly mention that there is a generated clock on the /2 register. The Launch Clock they're showing is this generated clock, which is treated like a data path to itself. The Latch Clock is the main clock feeding the /2 register. So all the waveforms are for analysis of the feedback path, not the path to the downstream register.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Rysc,

    thanks for your response.

    and then both the launch edge and the latch edge for setup/hold analysis should be from the the main clock feeding the /2 register , right?

    thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    No, the /2 clock comes out of the .q of the register, but the register actually latches it in on what drives the .clk, which is the /1. So the "clock is data" on both edges of the output clock, but the latch clock only clocks it in on its rising edge(which all happen to coincide in this example).

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I see. thanks.

    by the way, I also am learning your 《TimeQuest_User_Guide》Wiki Release 1.1. Do you have updates on it now? Thank you for your great efforts.

    BR,

    Fisher Cheng
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    No updates, but I did put together a separate document on source-synchronous interfaces. I actually plan on updating it again this week.