About altera_pll in quartus 15.1.0.185

You have to edit my_project_run_msim_rtl_vhdl.do into simulation/modelsim directory.

transcript off
if ! {
	file mkdir bemicro-cv-a9_iputf_libs
}
if {} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vcom "C:/FPGA/project_dir/pll_sim/pll.vho"
if {} {
	vdel -lib pll -all
}
vlib pll
vmap pll pll
vcom -2008 -work pll {C:/FPGA/project_dir/pll.vhd}
vlog -vlog01compat -work pll +incdir+C:/FPGA/project_dir/pll {C:/FPGA/project_dir/pll/pll_0002.v}
vcom -2008 -work work {C:/FPGA/project_dir/my_file.vhd}
#  .. VHDL files
vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L rtl_work -L work -voptargs="+acc"  top_tb +nowarnTFMPC
#  where top_tb is testbench file to run