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Honored ContributorAbout altera_pll in quartus 15.1.0.185
Folks, help me please! I lost few days from my life. I not sleeping and reading manuals..... I have simple question.
I create simple project, based on altera_pll with default megawizard settings. 2 input pins(clk & reset) and 2 out pins (out & locked). Problem in functional simulation this simple theme in latest version of Quartus. In prev version - all seems to be working. Folks, explain if possible this situation. Problem is my own hands or this is software bug? I have this: $ cat transcript # OpenFile ydpll.vho# Load canceled vlib work vcom -reportprogress 300 -work work /home/triod/yd/ydpll_sim/ydpll.vho# Model Technology ModelSim ALTERA vcom 10.4b Compiler 2015.05 May 27 2015# Start time: 23:39:22 on Nov 20,2015# vcom -reportprogress 300 -work work /home/triod/yd/ydpll_sim/ydpll.vho # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Loading package altera_lnsim_components# -- Compiling entity ydpll# -- Compiling architecture RTL of ydpll# End time: 23:39:22 on Nov 20,2015, Elapsed time: 0:00:00# Errors: 0, Warnings: 0 vsim work.ydpll# vsim work.ydpll # Start time: 23:39:36 on Nov 20,2015# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading altera_lnsim.altera_lnsim_components# Loading work.ydpll(rtl)# Loading sv_std.std# ** Error: (vsim-3733) /home/triod/yd/ydpll_sim/ydpll.vho(303): No default binding for component instance 'ydpll_altera_pll_altera_pll_i_639'.# The following component generic is not on the entity:# PLL_CTR_RESYNC# Time: 0 ps Iteration: 0 Instance: /ydpll/ydpll_altera_pll_altera_pll_i_639 File: nofile# Error loading design# End time: 23:39:37 on Nov 20,2015, Elapsed time: 0:00:01# Errors: 1, Warnings: 0 [ydpll_sim]$ My test project attached.9 Replies
Altera_ForumSince previous version work, you can use it as workaround for the time being. If same design pass in old version but fail in newer version. You can file a service requets to MySupport.
- Altera_Forum
I can confirm that problem.
Simulation models of PLLs generated with Quartus (both 15.0 Web Edition and 15.1 Lite Edition) - do not work with Modelsim ALTERA STARTER EDITION 10.4b - but do work with Modelsim ALTERA STARTER EDITION 10.3d I get an error message as described above as well. Is there a service request for that already? - Altera_Forum
You have to edit .do file in simulation folder
- Altera_Forum--- Quote Start --- You have to edit .do file in simulation folder --- Quote End --- Sorry, but I have to do what?
- Altera_Forum
You have to edit my_project_run_msim_rtl_vhdl.do into simulation/modelsim directory.
This is an example of working file:
You have to verify that pll_sim directory path is righttranscript off if ! { file mkdir bemicro-cv-a9_iputf_libs } if {} { vdel -lib rtl_work -all } vlib rtl_work vmap work rtl_work vcom "C:/FPGA/project_dir/pll_sim/pll.vho" if {} { vdel -lib pll -all } vlib pll vmap pll pll vcom -2008 -work pll {C:/FPGA/project_dir/pll.vhd} vlog -vlog01compat -work pll +incdir+C:/FPGA/project_dir/pll {C:/FPGA/project_dir/pll/pll_0002.v} vcom -2008 -work work {C:/FPGA/project_dir/my_file.vhd} # .. VHDL files vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L rtl_work -L work -voptargs="+acc" top_tb +nowarnTFMPC # where top_tb is testbench file to run - Altera_Forum
Was there a solution to this? I'm getting...
** Error: (vsim-3733) H:/work/PROJ/CJLp/source/pll_85m_sim/pll_85m.vho(303): No default binding for component instance 'pll_85m_altera_pll_altera_pll_i_639'.# # The following component generic is not on the entity:# PLL_CTR_RESYNC# Time: 0 ps Iteration: 0 Instance: /cjlp_tb/uut/u_pll/pll_85m_altera_pll_altera_pll_i_639 File: nofile# Loading work.pll_10m(rtl)# ** Error: (vsim-3733) H:/work/PROJ/CJLp/source/pll_10m_sim/pll_10m.vho(305): No default binding for component instance 'pll_10m_altera_pll_altera_pll_i_1098'. for the three different pll's I'm using. I've checked that the paths are correct like suggested. There is no PLL_CTR_RESYNC generic anywhere as it's complaining about? I'm also using quartus 15.1.0.185 with ModelSimAE. It's like it's not picking up the right underlying model. - Altera_Forum
The error is NOT that you are missing a PLL_CTR_RESYNC generic on the altera_pll entity, the problem is that there is an PLL_CTR_RESYNC generic on the iopll_bootstrap component down inside the altera_lnsim_components.vhd file.
I found a solution to this by editing the altera_lnsim_components file. Find the following: component iopll_bootstrap generic( PLL_CTR_RESYNC : integer := 1; PLL_AUTO_RESET_ON_LOSS_OF_LOCK : integer := 0 ); Comment out the PLL_CTR_RESYNC generic and recompile both this file and your PLL. That should get you past your issue. - Altera_Forum
I'm running into exactly the same error. I'm using Quartus 15.1.0 and ModelSim 14.0b Altera Starter Edition on an Linux.
But I can't find the altera_lnsim_components.vhd file mentioned in the post above to comment out the PLL_CTR_RESYNC : integer := 1; line. Are there any more experiences/suggestions on that topic. I can't believe that this is a Quartus Bug, as there are so few results when searching for this issue on the forum... - Altera_Forum
