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hzsk_csc's avatar
hzsk_csc
Icon for New Contributor rankNew Contributor
2 years ago

Abnormal waveform output from fir ii IP core

I am currently developing a filtering project using MAX 10 FPGA and Quartus Prime 17.1 development software。The filter is prepared to use the fir ii IP core to filter out frequencies above 500Hz. Th...
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi,


It seems you are having clock rate and sampling rate mismatch issues. CLK RATE is 50MHz and Sampling rate is 10ksps and my understanding is that you are capturing or simulating FIR output at 50MHz can you capture the samples and do the PWELCH in MATLAB at 10ksps and check are you getting 25Hz?


Also, to confirm mismatch issue can you please try to make CLK and sampling rate same and then do the simulation.


And if still does not resolve the issue please share your project. I will look into it.


Thank you,

Kshitij Goel


FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

I guess that ast_sink_valid isn't correctly driven by the sample rate. As suggested show your code, at least filter instantiation.

Filter output options can be optimized, you have unused MS bits and insignificant LS bits. If coefficients are copied 1:1 from Matlab design, 3 MS bits can stripped in "saturation" mode to achieve unity gain, output would be usually truncated to 16 - 24 bits by stripping respective LS bits.