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Hi,
I would use the post-synthesis netlist, because there you have all node which "survived" the synthesis. An other option is to preserve the node. You cando that with the attribute
wire keep_wire /* synthesis keep */; for verilog
signal keep_wire : std_logic;
attribute keep: boolean;
attribute keep of keep_wire: signal is true; for VHDL
Kind regards
GPK
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Ah, Thank you so much! I really appreciate your help! :)
I only remember that there is a way to keep the registers from being synthesis away. There is really a way to keep a wire during synthesis. Thank you! I will try!
By the way, " /* synthesis keep */" is just suitable for quartus II only or can be used even in other software?
Honored Contributor
