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Hi, pletz. Thank you for showing me the way.
I tried the assignment editor just now, but when I assign the output pin of the gating cell as a global clock, it shew in yellow(The Help tells that the node I am trying to specify is not found in the netlist), But I really found the pin in the node finder! ( The filter is set to pre-synthesis)
And after compilation, the report shows that it is still not using the global routing resource(there is still enough global resource left).
Is it that I should not search that pin in the pre-synthesis netlist? Then which type of netlist should I use to specify as a global clock? Please help me.
Now I have to constrain the output of the gated clock as a new clock in my '.sdc' file. And this time it worked.
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Hi,
I would use the post-synthesis netlist, because there you have all node which "survived" the synthesis. An other option is to preserve the node. You cando that with the attribute
wire keep_wire /* synthesis keep */; for verilog
signal keep_wire : std_logic;
attribute keep: boolean;
attribute keep of keep_wire: signal is true; for VHDL
Kind regards
GPK
Honored Contributor
