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Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- Hi, if you have an clocked register Quartus has to check whether the setup and hold time requirements of the register are fullfilled.The input data needs to be stable a certain time before (setup time) and it must be stable a certain time after (hold time) the active clock edge. Your first violation is a hold time violation. That means your data coming out of the register ( it takes a certain time to propagate the signal to the out of the register, it's call tco) through the multiplexer logic is too fast. The data is not long enough stable. You got 5 paths listed, because the timing analyzer found 5 different paths from node count[1] to node AVE[9]. Kind regards GPK --- Quote End --- Hi, pletz, thank you so much. I think I understand what is going on now! Thank you so much. I will check the 5 different paths. And good news is, the hold violation disappear after recompilation. Thanks again for your help. I learned so much today:) Best Regards.