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You have a loop in the path:
- HSYNC_D value is assigned to HSYNC with registered sync logic, namely at clk edge
- HSYNC is assigned to HSYNC_D constantly, through combinatorial logic.
You have a hold violation because the delay from combinatorial logic is lower than the register hold requirement, so its status could be undefined.
In order to eliminate the timing violations you should add some delay to the combinatorial path.
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Hi, Cris72 Thank you for your answer:)
I still have a problem about it. I always thought that it will not check the path "between" the same sequential element.
I think that the active clock edge should have no skew at the clock port of the same register. Am I right? Please, I am a little confused......
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