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does it increase the power when using enables this way instead of a 1KHz clock
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Basically, yes. With a reasonable system clock (e.g. 50 MHz), it isn't a problem with usual designs. Furthermore, operating consderable parts of a design with 1 kHz clock frequency is rather a lab exercises problem than a typical situation of real world FPGA design.
Generally, you're free to use ripple clocks if they are helpful to save power. But in most designs, these slow clock domain partitions have to cooperate with other design parts. Timing closure of domain crossing signals will become much more difficult with ripple clocks. That's why their usage is discouraged.
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