A simple answer if there is one (please)

Your clock divider as such should work as well, although it divides by 50001.

The problem is in using PADDLE_CLOCK in an edge sensitive expression. It's a formed by combinational logic and has glitches. Making PADDLE_CLOCK a register and assigning it inside the posedge block would avoid this problem. But it's still a ripple clock, delayed in relation to CLOCK_50. The problem arises with signals, that are used in both clock domains CLOCK_50 and PADDLE_CLOCK. Using PADDLE_CLOCK as a clock enable instead keeps one clock domain for the design.