A simple answer if there is one (please)

Perfect, no more warnings and I appear to be able to "export" the result for want of a better phrase :

reg [15:0] paddleCount = 16'd0;

reg PADDLE_CLOCK;

always @(posedge CLOCK_50)

begin

if (paddleCount)

begin

paddleCount <= paddleCount - 16'd1;

PADDLE_CLOCK <= 1'b0;

end

else

begin

paddleCount <= 16'd49999;

PADDLE_CLOCK <= 1'b1;

end

end

always @(posedge PADDLE_CLOCK)

begin

etc

I'm still not sure why the original didn't work - was it the "wire" as opposed to the "reg"?

wire PADDLE_CLOCK;

assign PADDLE_CLOCK = (paddleCount == (16'd50000));

always @(posedge CLOCK_50)

begin

if (PADDLE_CLOCK)

paddleCount <= 16'd0;

else

paddleCount <= paddleCount + 16'd1;

end

Many thanks for your help

Lomax