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Altera_Forum's avatar
Altera_Forum
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16 years ago

A simple answer if there is one (please)

Dear All, I've read in multiple posts etc that I'm not allowed to use ripple clocks etc but would anyone be so kind as to give me the actual Verliog code (without using a PLL) for how to produ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Divide 50 MHz by 50000 and get a signal that's '1' for one clock period and '0' for 49999. Use it as clock enable in a synchronous process, that's clocked by the 50 MHz as well.

Clock enable means e.g. 

always @(posedge clk50)
begin
  if (cnt_1kHz)
    begin
      cnt_1kHz--;
      ce_1kHz <= 1'b0;
    end
  else
    begin
      cnt_1kHz <= 16'd49999;
      ce_1kHz <= 1'b1;
    end;
  if (ce_1kHz)
    begin
      // This code executes at 1 kHz speed
    end
end