a question in quartus

You are getting on track but there are some issues:

Quartus error seems to do with your operating system. There is a recent thread about working around it.

your state machine isn't there yet in the code.

some syntax issues, clk in sensitivity list but unused. your process :is it combinatorial or sequential?

if(state = state1) then

....

else -- no need for if state = state2

loop from 0 to 127 not 0 to 128

so you are basically switching the inputs to adders and takingoutputs...fair enough. You will need to use memory for your matrix: here you got resource issue. As FvM said you can't use 64k registers in logic. You need to use memory of fpga. Then your access is limited to your address buses.

Can you post the functional requirements of your work(forget about implementation)

some points I can't understand

1.what do you mean by is the process sequential or combinational? isn't a process sequential always?

2.you told me before that when compiling the for loop the only effect if i was using one wire will be last one right? so in this case when i am using 128 computation engines doesn't this mean that only last 128 will have effect since I have 128 wires in this case?

3.now do you mean i have to create ram memory(using megafunction wizard or any way) instead of using these registers and dealing with addresses?:( or dealing with fpga kit memory which also i am not familiar with it very much?(I have startix 3 devolpment kit)

4.what do you mean by functional requirements?

1) a process is always sequential as a code body but it results in either logic(seq or comb). However this is a side issue and don't worry about it. All I want to say now is your process should be clked.

state machine: if you only need two states then just toggle a signal and avoid the headache of state machine...

2) your loops now are ok, I just pointed to the fact that the index to be 0 to 127 or 1 to 128(whichever suits your indexing).

3) yes you need to think of a plan to use memory, unless you ease up the matrix size. why not use 8 bits instead of 32 bits

4) by functional I mean: what is that wany to do in terms of algorithms.

The crucial point in your plan must be the speed of processing versus incoming data in order to allow for sharing resource, otherwise you will end up in serious resource problems.

1) in the first part where i construct my frames i should use clock since the input depend on the clock but once the frames are constructed I should finish all computations before 192 clocks which is the time of constructing the new frames

2)i understand that i was wrong the loop will be 0 to 127 ok but i am speaking about another u told me before in implementing this loop

for i in 0 to 255

wire1<=a(i);

wire2<=b(i);

c(i)<=wire3;

end loop;

only last loop will be taken into consideration right?

so doesn't this mean similary when creating 128 wires in 256 loop that only last 128 values will have effect

3)i can't use 8 bits since first value of alpha should be intialized to infinity which will be normalized to 10^5 in my case or any very large number i choose which give the design less probability of error.any suggestion in this problem will be useful

4)what i want to do is a very long and complicated algorithm if u want me to explain it just ask me and i will try to simplify it for you

Thank u so much

I didn't say last loop is valid but last drive on any node i.e. last assignment to same target within one loop. since your targets now are different in each assignment(per state) no problem.

Is there any chance to avoid constructing frames inside fpga. I mean can you index your input samples as they come in or do you have to save them.

You can also think of two parallel storage(too much but may help) i.e. store an incoming frame while processing the one already received then swap over.

This may give more time.

if you need 192 clks to finish off one frame then how fast is this clk. It is the actual frequency(or available time) that matters now in order to estimate what fmax can you lift up to.

i will try to explain the idea simply

the idea of turbo code is constructing encoder and decoder and some helping blocks how is that done in matlab that's what i will try to explain so please be patient.

a random frames is created each of length 256 (stream of ones and zeros this is the original message) the rate of the turbo code is 1/3 this means that for each one bit input there will be 3 bits(first is systematic second is parity1 and third is parity2 each one of the three is 256) output so after entering 256 input frame there will be 768 bits(plus 12 tail bits which i don't use but it helps in returning the encoder to zero state again to start encoding next frame) i will then modulate each 4 bits to prodce I and Q(16 QAM) after that noise is added and so a block to compute soft values probability of the corresponding I and Q which means that i will use a lookup table in this operation where for each 2 available combinations of I and Q(according to my floating point resolution) there will be a corresponding probability for each 4 bit (ofcourse these probabilities is computed using certain design equation) and those 4 bits will be the input to the decoder so in each clock there will be 4 probabilities as input to the decoder for example in the first clock

P4=-14.6 P3=26.45 P2=67.35 P1=-0.463 where the sign represent wether this bit is zero or one and the value represent the coonfidence of this bit

in vhdl these floating point nubers is represented in 32 bits.

to construct first frame which is systematic bit [P4clk1 P1clk1]

parity1=[P3clk1] parity2=[P2clk1] in the next clock systematicbit=[P4clk1 P1clk1 P2clk2] parity1=[P3clk1 P4clk2 P1clk2] parity2=[P2clk1 P3clk2] and so on. This is the operation of constructing the 3 frames it's done for 192 clocks where after 192 clocks by using same sequence each frame will be at the end of clk 192 of length 256.Notice that another 3 clocks should be wasted to ignore the 12 tail bits(the input is ignored in those clocks).

let's say that this was the first input frame using this frame i should do my computation. Surely the computation on the first frame is done while receiving second frame simultaneously and computation should be done before buffering the second frame in order to start operating on the second frame. Now let's go through the algorithm, i will try to explain it using ideas in matlab there will be 2 decoders which operate in iterative way now let's define some matrices for both decoders gamma,alpha,beta and llr. gamma,alpha and beta is (8*256) while llr is (1*256). Through some equations we can compute gamma for example the equation of gamma is

gamma_decoder1(i)=0.5(Lc*systematic(i)*u_k+x_k*parity1(i)+llr1(i)) where x_k and u_k is one or negative one according to state diagram known by both encoder and decoder so in the same moment (same i) we will have 8 states so at the last the gamma will be (8*256) using this gamma we compute alpha and beta where alpha and beta equations use gamma computed and the alpha in the past moment for example alpha(i=1,state=3)=maximum(alpha1(i=0,state=3)+gamma_input0(i=0,state=3),alpha1(i=0,state=3)+gamma_input1(i=0,state=3)) notice that the alpha is intialized by alpha(i=0,state0)=0,alpha(i=0,state1)=0,alpha(i=0,state2)=0,......................alpha(i=0,state8)=-infinity until llr of decoder 2 is computed which affect the computation og gamma of decoder 2 hence it's alpha, beta and llr of decoer one this is called a complete iteration now to go through the next iteration decoder one uses llr generated by decoder 2 and so on for a fixed time of iterations.at last by observing the llr1 and llr2 we can dicide wether this bit is one or zero according to certain equations. Certainly those iterations should be carried out in less than 192 clocks the time of constructing the second frame pretty fun hah ;), hope u got the picture.

now if u don't have time or will to understand the decoder i will answer your questions :)

I should save the inputs using state machine with 3 states because the ordering of the input is not constant but changes according these states

I can't understand parallel storage idea isn't that what i am already doing i store the frame while operating on the previous one. that's what i am doing.

I think yes I should know my fmax but I should first know the delay of all computation engine blocks to do that.

I think now the main problem will be the memory issue and the fact that i can't use registers for that much of data if we assumed that the program will run correctly since i am getting a nasty error that i can't figure out which is

Error: Out of memory in module quartus_map.exe (2141 megabytes used)

Error: Current module quartus_map ended unexpectedly

i have posted earlier a thread asking for help and i have been given a link where there should be the solution to my problem but the link seems to be broken and not working

http://www.microsoft.com/whdc/system...ae/paemem.mspx (http://www.microsoft.com/whdc/system/platform/server/pae/paemem.mspx)

So far I can imagine the input side:

1) you receive your input bits, store the first 256 bits in logic or memory(no problem) [input frame# 1).

2) you now do two things: process above frame 1 while receiving next 256 bits in another location(no problem)(input frame# 2).

you need 192 clks(at input rate I presume) to finish processing input frame# 1 to end up with 3 internal frames(256 x 3). This should be no problem if your input frame# 2 takes 256 clks to arrive completely(if you are receiving it serially), otherwise you obviously have to go faster than input rate.

3) you then convert every 4 bits of frame 768 ??? to an IQ pair, add noise and get 4 probabilty values for each pair from somewhere...thereafter it is not clear to me. If you describe your work sequentially in short bullets may help.

Is it one matrix(size 8x256x32) that you need or two? still why not lower probability from 32 bits to less because you might be just wasting the precision internally.