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Altera_Forum
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12 years ago

A question about vector port declaration

I have a question about port declaration which confuses me: In VHDL, for ports or signals, we can define as: A : out std_logic_vector(0 to 15); signal B,C : std_logic_vector(7 downto 0)...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks, Kaz. But for:

A(0 to 7)<=B;

Is A(0) <= B(7), or it is still A(0) <= B(0) ? It is very confusing. Some IP ports design is very annoying!

Thanks.