A question about vector port declaration

To make it easy to understand and be absolutely sure, I would say: why won't you just write it down the way you want it to be. So if you want to do

A(15 downto 8)<= B;

A(7 downto 0) <= C;

That's what you write down, if you want it the other way, you write it the other way.

But for the statement itself I would assume it means the first one, but I'm not sure.

To be sure you could always try to put some known values in it and see what happens

*edit*

Oops sorry misread the question, ignore this message, I'm sorry for the inconvenience

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I have a question about port declaration which confuses me:

In VHDL, for ports or signals, we can define as:

A : out std_logic_vector(0 to 15);

signal B,C : std_logic_vector(7 downto 0);

I personally prefer the 2nd one but sometimes IP or modules from other engineers may be defined in 1st style. Now I have a question:

if I do:

A<=B & C;

Does this operation do is:

A(15 downto 8)<= B;

A(7 downto 0) <= C;

Or is:

A(15 donwto 8) <= C;

A(7 downto 0) <= B;

or neither of them?

Thanks in advance.

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neither.

As far as I know the location of bit (not the index) defines its weight in the bus.

thus

A <= B&C; means A(0 to 7) <= B, A(8 to 15) <= B

but the compiler may not accept this assignment.

so it is always better to use 15 downto 0 to avoid bit index confusion

Thanks, Kaz. But for:

A(0 to 7)<=B;

Is A(0) <= B(7), or it is still A(0) <= B(0) ? It is very confusing. Some IP ports design is very annoying!

Thanks.

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Is A(0) <= B(7), or it is still A(0) <= B(0) ? It is very confusing. Some IP ports design is very annoying!

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It's A(0) <= B(7), as kaz said, it's copied according to the position, leftmost to leftmost, etc.

If you want to copy B(0) to A(0), you'll use a for loop.