A question about vector port declaration

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I have a question about port declaration which confuses me:

In VHDL, for ports or signals, we can define as:

A : out std_logic_vector(0 to 15);

signal B,C : std_logic_vector(7 downto 0);

I personally prefer the 2nd one but sometimes IP or modules from other engineers may be defined in 1st style. Now I have a question:

if I do:

A<=B & C;

Does this operation do is:

A(15 downto 8)<= B;

A(7 downto 0) <= C;

Or is:

A(15 donwto 8) <= C;

A(7 downto 0) <= B;

or neither of them?

Thanks in advance.

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neither.

As far as I know the location of bit (not the index) defines its weight in the bus.

thus

A <= B&C; means A(0 to 7) <= B, A(8 to 15) <= B

but the compiler may not accept this assignment.

so it is always better to use 15 downto 0 to avoid bit index confusion