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Honored Contributor
Honored ContributorA question about the asynchronous clear signal of dual clock FIFO
Hi, I used a MegaWizard generated dual clock FIFO in a design. FIFO width is 16 bits and its depth is 2048. The write and read clock of this FIFO is 90 MHz and 60 MHz respectively. Both of the...
Altera_ForumHonored Contributor
Honored ContributorThe important part is correct: "if there are several idle clock between the de-assertion of aclr signal and write operation, this timing violation doesn't matter and can be just ignored."
The first part as to why is not. It's saying that the reset de-assertion, which is driven by a clock edge, can't reach all the destinations in one clock cycle. So it's not the data in the fifo or anything like that, but the actual reset signal. Go to www.alterawiki.com and search for the TimeQuest User Guide. I did a write-up on recovery/removal violations there.
