A question about the asynchronous clear signal of dual clock FIFO

The important part is correct: "if there are several idle clock between the de-assertion of aclr signal and write operation, this timing violation doesn't matter and can be just ignored."

The first part as to why is not. It's saying that the reset de-assertion, which is driven by a clock edge, can't reach all the destinations in one clock cycle. So it's not the data in the fifo or anything like that, but the actual reset signal. Go to www.alterawiki.com and search for the TimeQuest User Guide. I did a write-up on recovery/removal violations there.