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Honored Contributor
Honored ContributorA question about the asynchronous clear signal of dual clock FIFO
Hi, I used a MegaWizard generated dual clock FIFO in a design. FIFO width is 16 bits and its depth is 2048. The write and read clock of this FIFO is 90 MHz and 60 MHz respectively. Both of the...
Altera_ForumHonored Contributor
Honored ContributorDoes this Recovery timing violation mean some data in the FIFO can not be cleared in one period of 90 MHz write clock?
Assuming the write operation is started on the next clock edge right after the de-assertion of aclr signal, this recovery timing violation will lead to logic error. But, if there are several idle clock between the de-assertion of aclr signal and write operation, this timing violation doesn't matter and can be just ignored. Is my understanding right?
