a problem with gate-level simulation of stratix3

when i implement a gate-level simulation of stratix3 device ,

with quartus 8.1 and modelsim 6.3g,

i came across six document:

pll_dco_3_1100mv_0c_slow.vo

pll_dco_3_1100mv_85c_slow.vo

pll_dco_min_1100mv_0c_fast.vo

pll_dco_3_1100mv_0c_v_slow.sdo

pll_dco_3_1100mv_85c_v_slow.sdo

pll_dco_min_1100mv_0c_v_fast.sdo

(pll_dco is the project name)

i have not met these documents,

(only kowns <project name>.vo

and <project name>_v.sdo)

Thanks!

i want ask :

what are their usage,

and the method to use them.