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Altera_Forum's avatar
Altera_Forum
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15 years ago

A little help please...

I am a recent convert to Altera from Xilinx (hush my mouth) but my last design was in 1994. I have a few questions that just don't seem to be answered in simple terms :

1. Say I have a schematic (.bdf) with 50 i/o pins all labelled. I then convert to a symbol (.bsf) and insert on top level sheet. Do I have to attach labelled pins for all of the i/o on the top level sheet also?

2. I am embedding a NIOS II processor. I have used an example that came with a development board (Cyclone II) which has a PIO 8 outputs). Now I have added another PIO (8 inputs) and hit "Generate". All is fine except when I convert the NIOS II schematic to a symbol it has an extra "ds_MISO_from_the_epcs_controller" that wasn't there originally (The EPCS controller was, but there was nothing on the symbol block). Can I safely ignore it, and if so how do I not display it on the symbol.

3. I am putting a lot of work into this. Can I safely assume that the Quartus web version (free) will not ask me for $$ or time limit or anything like that?

Andrew

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    For 1, you can right-click -> Generate Pins for Symbols. All the I/O will be added to that top-level.

    For 3., there won't be anything new. Some features and devices are not enabled with the web editiion, but it's not like something will become disabled.

    Not sure on 2.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thank-you that was helpful...but to keep the top level uncluttered, iis it compulsory to regenerate the i/o pins on the top level symbol or can I leave the pins one layer down?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Only ports on the top-level will connect to I/O. If you don't hook them up, they will be considered hanging(unless you give them a default) and will be synthesized out. Basically, yes.