8 bit counter veriloge code

Dears I designed a counter with clock_in and clock_out which display the output on Leds but I cold not display it on 7-segment, if someone have any idea for that help

the code is :

module updowncounter (updown ,count,enable,reset,clkin,clk_out);

input enable, updown;

output [3:0] count= 4'b0000;

reg [3:0] count;

input clkin,reset;

reg [32:0] count_reg=0;

reg clk_out=0;

output clk_out;

always @ (posedge clkin)

if (count_reg<10000000)

count_reg <= count_reg+1;

else

begin

count_reg <= 0;

clk_out <= ~clk_out;

end

always @( posedge clk_out )

if (updown && enable && reset )

count = count + 1;

else

if (!updown && enable && reset)

count = count -1;

else if(!reset)

count = 4'b0000;

//always @ (posedge clkin)

//begin

// end

endmodule

I have wrote the code of converting the counter output as below but I dont know how can i connect it in one module to display:

module updowncounter (updown ,count,enable,reset,clkin,clk_out);

input enable, updown;

output [3:0] count= 4'b0000;

reg [3:0] count;

input clkin,reset;

reg [32:0] count_reg=0;

reg clk_out=0;

output clk_out;

always @ (posedge clkin)

if (count_reg<10000000)

count_reg <= count_reg+1;

else

begin

count_reg <= 0;

clk_out <= ~clk_out;

end

always @( posedge clk_out )

if (updown && enable && reset )

count = count + 1;

else

if (!updown && enable && reset)

count = count -1;

else if(!reset)

count = 4'b0000;

//always @ (posedge clkin)

//begin

// end

endmodule