74LS series in Quartus ?

The existing 7400 series components are not timing equivalent with old 7400 series. FPGAs have a different place-and-route every compile, and hence the timing changes every time you compile(assuming something in the design has changed. The basic compile is deterministic). On top of that, the device and speed grade you choose will cause timing to vary. So there is no reason to have the LS devices, since timing is not guaranteed. The way users deal with their variance is enter timing constraints, i.e. this clock is running at 20ns and this I/O drives another device that is clocked by the same 20ns clock and has a Tsu of 7ns. Then place-and-route will try to meet those requirements, and static timing analysis will tell you if it did or not.

That all being said, I imaging anything you put into a current design will be significantly faster than 74LS timing. (And being too fast can occasionally be a problem, but most issues are from being too slow.)