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CFabr1
New Contributor
5 years agoThanks for reply.I'm not targeting Intel FPGAs but old Altera CPLDs.The transceiver is connected to the the data bus of an external RAM hence, even if I desgn my own transceiver, then I have the problem of how to interface the RAM to internal logics of the CPLD.Sorry but I'm new to HDL and all I can do for now is doing designs using schematics block (which is not the same thing of writing HDL hence it could not work)