4 bit Ring Counter

Alright I really need help on this.I have installed the 13.4 Xilinx version and I have a code for a 4 bit ring counter and its testbench. When I try implementing the code I get those errors:

ERROR:Security:11 - No 'xc7a8' feature version 2012.01 was available for 'ISE',

ERROR:Map:258 - A problem was encountered attempting to get the license for this

architecture.

. The code used for the counter is:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity ring_counter is

port (

DAT_O : out unsigned(3 downto 0);

RST_I : in std_logic;

CLK_I : in std_logic

);

end ring_counter;

architecture Behavioral of ring_counter is

signal temp : unsigned(3 downto 0):=(others => '0');

begin

DAT_O <= temp;

process(CLK_I)

begin

if( rising_edge(CLK_I) ) then

if (RST_I = '1') then

temp <= (0=> '1', others => '0');

else

temp(1) <= temp(0);

temp(2) <= temp(1);

temp(3) <= temp(2);

temp(0) <= temp(3);

end if;

end if;

end process;

end Behavioral;

I think that i need to adapt the code for this newer version of Xilinx but im not sure how to do that.Or what do I need to change in it to adapt it to the new version?

The code is written and simulated in Xilinx 10.1 which I cannot find anymore.

Thanks a lot!