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PonPon's avatar
PonPon
Icon for New Contributor rankNew Contributor
1 year ago

2DFF synchronizer output was determined to be a clock by timing analyzer

Hello everyone, I'm the newbie in FPGA. I want to design a frequency counter, so the design will involved some CDC problem. Therefore, I used FIFO(I use the quartus fifo ip) and 2DFF synchronizer i...
Timing
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


May I know does your problem resolved with create_generated_clocks?


If the syncrhonizer Din and Qout clock is the same then you probably not need the clock relationship, constraint like below will do:

create_generated_clock -name <custom name> -source <input to synchronizer> <output of synchronizer>