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PonPon's avatar
PonPon
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1 year ago

2DFF synchronizer output was determined to be a clock by timing analyzer

Hello everyone, I'm the newbie in FPGA. I want to design a frequency counter, so the design will involved some CDC problem. Therefore, I used FIFO(I use the quartus fifo ip) and 2DFF synchronizer i...
Timing
sstrell's avatar
sstrell
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1 year ago

It depends on out_freq. You have to specify the properties of this newly generated clock.

create_generated_clock -name <custom name> -source <input to synchronizer> <output of synchronizer> <output clock relationship to source>

PonPon's avatar
PonPon
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1 year ago
I’m not really sure about the properties of this clock, can you tell me more information?

out_freq will go into the 2DFF synchronizer, and then the synchronizer output this clock, I only know about this.
  • sstrell's avatar
    sstrell
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    1 year ago

    What is the frequency of out_freq? You have it coming from an outside signal Fin then go though something you've named div2 so there's no way for me to know what the properties of this signal are.

    • PonPon's avatar
      PonPon
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      1 year ago
      In my constraint, fin will be a 80kHz signal , so the out_freq which be dived by 2
      becomes a 40kHz signal.
    • PonPon's avatar
      PonPon
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      1 year ago
      And I do this constraint because I want to measure the FM signal which frequency is between 55kHz~75kHz.