Forum Discussion
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- Is it possible to have this array in VHDL? --- Quote End --- No. You could use an array if you changed your format [i][j] = [1][numvalid, sample1, sample2, sample3, 0 , 0 ] [2][numvalid, sample1, sample2, sample3, sample4, sample5] [3][numvalid, sample1, sample2, 0 , 0 , 0 ] or you can use a list of lists (or an array of lists). You'll have to be careful if you're using this for synthesis though. Cheers, Dave