Forum Discussion

HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
6 years ago

2D Array in Verilog is Synthesizable (Using Quartus)?

Hi,

localparam [15:0] SYMBOL_OS [0:7] = { 16'h0A, 16'hA0,16'h1A, 16'hA2, 16'h1F, 16'hA5, 16'h58, 16'h93 };

I have above 2 dimensional array in one of my verilog module. Whether above statement is synthesizable with Quartus?

FYI, when I simulate (using Modelsim), I need to write the above Symbol declaration as

localparam [15:0] SYMBOL_OS [0:7] = ' { 16'h0A, 16'hA0,16'h1A, 16'hA2, 16'h1F, 16'hA5, 16'h58, 16'h93 };

With Regards,

HPB

1 Reply

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    You can use 2D array in the Intel Quartus Prime software.

    Synthesis tools typically consider all signals and variables that have a multi-dimensional array type and then create a RAM block, if applicable. This is based on the way the signals or variables are assigned orreferenced in the HDL source description.

    Thanks.