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HBhat2
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6 years ago

2D Array in Verilog is Synthesizable (Using Quartus)?

Hi, localparam [15:0] SYMBOL_OS [0:7] = { 16'h0A, 16'hA0,16'h1A, 16'hA2, 16'h1F, 16'hA5, 16'h58, 16'h93 }; I have above 2 dimensional array in one of my verilog module. Whether above statement is...