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Altera_Forum's avatar
Altera_Forum
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12 years ago

2 to 1 mulltiplexer

Hi all. I have problem during run VHDL code for 2 to 1 multiplexer. this multiplexer have 8 bit for input and output. while the select bit is only one bit. Here is my coding. However, there is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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I want to ask question. Is it possible if I still want used this code "LEDR <= (NOT (s) AND SWX) OR (s AND SWY);" in my architecture? Is there any method to use it. Or is not possible?

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The above code is asking the synthesis tool to do that for you. What the tool will do is essentially what you have written, but it needs to happen on a per bit basis, eg., 


process(s,SWX,SWY)
begin
   for i in 0 to 7 loop
      LEDR(i) <= (SWX(i) and (not s)) or (SWY(i) and s);
   end loop;
end process;

Note how this code loops over each bit in the 8-bit word.

Cheers,

Dave