1:8 demultiplexer using two styles behavioral and structural modeling

library ieee;

use ieee.std_logic_1164.all;

entity inv_6 is

port(a:in std_logic; b:out std_logic);

end entity;

architecture beh1 of inv_6 is

begin

b<= not a;

end beh1;

library ieee;

use ieee.std_logic_1164.all;

entity nand_8 is

port(k1,k2,k3:in std_logic; z:out std_logic);

end entity;

architecture beh2 of nand_8 is

begin

z<= ((k1) nand (k2) nand (k3));

end beh2;

library ieee;

use ieee.std_logic_1164.all;

entity and_1 is

port(c1bar,c2bar,c3:in std_logic; h:out std_logic);

end entity;

architecture beh3 of and_1 is

begin

h<= c1bar and c2bar and c3;

end beh3;