1:8 demultiplexer using two styles behavioral and structural modeling

library ieee;

use ieee.std_logic_1164.all;

entity demux1 is

port(a0,a1,a2,e1bar,e2bar,e3:in std_logic; y0,y1,y2,y3,y4,y5,y6,y7:out std_logic);

end demux1;

architecture beh of demux1 is

component inv_6

port(a:in std_logic; b:out std_logic);

end component;

component nand_8

port(k1,k2,k3:in std_logic; z:out std_logic);

end component;

component and_1

port(c1bar,c2bar,c3:in std_logic; h:out std_logic);

end component;

signal i1,i2bar,i3bar,i4bar,i5bar,i6bar,i7bar: std_logic;

begin

u1:and_1 port map(e1bar,e2bar,e3,i1);

u2:inv_6 port map(a0,i2bar);

u3:inv_6 port map(a1,i3bar);

u4:inv_6 port map(a2,i4bar);

u5:inv_6 port map(i2bar,i5bar);

u6:inv_6 port map(i3bar,i6bar);

u7:inv_6 port map(i4bar,i7bar);

u8:nand_8 port map(i2bar,i3bar,i4bar,i1,y0bar);

u9:nand_8 port map(i5bar,i3bar,i4bar,i1,y1bar);

u10:nand_8 port map(i2bar,i6bar,i4bar,i1,y2bar);

u11:nand_8 port map(i5bar,i6bar,i4bar,i1,y3bar);

u12:nand_8 port map(i2bar,i3bar,i7bar,i1,y4bar);

u13:nand_8 port map(i3bar,i7bar,i5bar,i1,y5bar);

u14:nand_8 port map(i2bar,i7bar,i6bar,i1,y6bar);

u15:nand_8 port map(i1,i6bar,i5bar,i7bar,y7bar);

end beh;