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Altera_Forum
Honored Contributor
16 years agoTo be feasible with acceptable FPGA resource consumption, the FFT calculation must be performed sequentially. A for ... generate construct or a for ... loop iteration scheme don't provide sequential processing, it's very different to the meaning of loops in procedural programming as C.
You have to design the sequential processing and implement it in a clocked process by yourself. The Altera FFT core also provides a variable length selectable at runtime, the license is included with the Quartus subscription version.