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- Your external device supplies a 5-200 MHz clock.
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Yes
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- The delay from the external delay may also change.
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Yes
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- You plan to deal with this by changing the PLL configuration, to have a suitable output frequency and phase.
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Yes
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An interesting approach.
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Why? Am I trying to solve this problem in some kind of unusual way? :)
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Q1: Do you have discrete set of frequencies/delays or are you in a situation where anything is possible?
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Frequency can be any from the given range 5-200 MHz and 3 sets of delays (3 different external devices)
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Q2: Is your entire design running on that single PLL output clock or do you have multiple clocks?
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There are more clocks and other interfaces but data is passed to other clock domain by using dual clock FIFO. Does this make any difference?
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