.sdc for reconfigurable PLL

Let me summarize my understanding of your problem:

- Your external device supplies a 5-200 MHz clock.

- The delay from the external delay may also change.

- You plan to deal with this by changing the PLL configuration, to have a suitable output frequency and phase.

An interesting approach.

A couple of questions to narrow down the problem:

Q1: Do you have discrete set of frequencies/delays or are you in a situation where anything is possible?

Q2: Is your entire design running on that single PLL output clock or do you have multiple clocks?