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Honored Contributor
Honored Contributor.sdc for reconfigurable PLL
Hi, Here is my situation: I have created design which contains PLL with dynamic reconfiguration, and dynamic phase shift options. Input clk of PLL can change in range from 5MHz to 200MHz...
Altera_ForumHonored Contributor
Honored ContributorLet me summarize my understanding of your problem:
- Your external device supplies a 5-200 MHz clock. - The delay from the external delay may also change. - You plan to deal with this by changing the PLL configuration, to have a suitable output frequency and phase. An interesting approach. A couple of questions to narrow down the problem: Q1: Do you have discrete set of frequencies/delays or are you in a situation where anything is possible? Q2: Is your entire design running on that single PLL output clock or do you have multiple clocks?
