Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

.sdc for reconfigurable PLL

Hi, Here is my situation: I have created design which contains PLL with dynamic reconfiguration, and dynamic phase shift options. Input clk of PLL can change in range from 5MHz to 200MHz...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Here is a part for PLL constrains of my initial sdc file: 

create_clock -period 5 -name pll_inclk  
create_generated_clock 	-name  pll_outclk_c0 
					-source ] 
					-phase 0 ]

So i have project compiled with my initial PLL constrains. What should i do next? Should i create separate sdc files for case in which i am interested just for timing analysis or i can say that if my design meets timing in max frequency it should be OK in lover frequencies?