Honored Contributor
Honored ContributorSometimes it is necessary to read through the endless documents of Altera. It is a tedious job but it will pay off.
A first thing to do is to constraint your input and output clocks. So if you have an input clock of 50 Mhz (ie period is 20ns) the constraint command in the sdc file will be: 1. create_clock -name board_clk -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLK}] //CLK will be whatever name you gave to the clock port in your top design To constraint your PLL there is basically three approaches. The easiest would be to implement an automatic constraint for both input and output clocks. For this you need: 2. derive_pll_clocks Now, as long as your custom code doesn't contain other cores such as transceivers, clock muxes, clock muxes with enables.. etc, you don't need to do anything (if I am correct) as far as timing is concerned. However in some cases if you have output/input pins operating at high clock freq then you will need to perform input/output constraint commands at a further stage. Good to add 3. derive_clock_uncertainty Also don't forget to start your sdc file with setting your time format: 4. set_time_format -unit ns -decimal_places 3 I hope this will give the quick necessary to start working
