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AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
3 years ago
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.ip/.qip PLL how to disable sdc generation?

Hello, When I create a PLL IP via Quartus (22.4 pro), It also creates .sdc constraint for it which clashes with my .sdc constraint (duplicate point, not possible to set as async group ..). I could...
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  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    Unfortunately, we don't have a notification system in place. However, I can provide you with a ticket ID [15013771573] so that you can submit a new case and get an updates on this enhancement request status from the respective agent. This will allow you to inquire about the status of the request, whether it is planned, implemented, or rejected. I suggest requesting an update after approximately one year or so.

    It's worth mentioning that there is a backlog of enhancement requests on the engineering side, and resources are limited. This is the reason for the extended timeframe required.

    Thank you for your understanding.


    Best Regards,

    Richard Tan


sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

If you're trying to use set_clock_groups, can't you just add them to your top-level .sdc file which would override the PLL .sdc?