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AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
3 years ago
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.ip/.qip PLL how to disable sdc generation?

Hello, When I create a PLL IP via Quartus (22.4 pro), It also creates .sdc constraint for it which clashes with my .sdc constraint (duplicate point, not possible to set as async group ..). I could...
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  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    Unfortunately, we don't have a notification system in place. However, I can provide you with a ticket ID [15013771573] so that you can submit a new case and get an updates on this enhancement request status from the respective agent. This will allow you to inquire about the status of the request, whether it is planned, implemented, or rejected. I suggest requesting an update after approximately one year or so.

    It's worth mentioning that there is a backlog of enhancement requests on the engineering side, and resources are limited. This is the reason for the extended timeframe required.

    Thank you for your understanding.


    Best Regards,

    Richard Tan


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

I can check with the engineering team to see if they are okay with making the changes.

Before I make the request, could you help provide justification for why you want to skip the SDC generation?

You may provide details on the specific problem or limitation you faced, the benefits of this feature, or any additional feedback that may help.


Best Regards,

Richard Tan



AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
3 years ago

Thanks Richard.

I want to disable the SDC generation because I'm not able to make the different clock outputs of the PLL

asynchronous clock domain (due to the generated .sdc which define clock points in not async group).

I already do defined myself the PLL clock output and the clock domains.

Alex.