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AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
3 years ago
Solved

.ip/.qip PLL how to disable sdc generation?

Hello, When I create a PLL IP via Quartus (22.4 pro), It also creates .sdc constraint for it which clashes with my .sdc constraint (duplicate point, not possible to set as async group ..). I could...
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  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    Unfortunately, we don't have a notification system in place. However, I can provide you with a ticket ID [15013771573] so that you can submit a new case and get an updates on this enhancement request status from the respective agent. This will allow you to inquire about the status of the request, whether it is planned, implemented, or rejected. I suggest requesting an update after approximately one year or so.

    It's worth mentioning that there is a backlog of enhancement requests on the engineering side, and resources are limited. This is the reason for the extended timeframe required.

    Thank you for your understanding.


    Best Regards,

    Richard Tan


AEsqu's avatar
AEsqu
Icon for Contributor rankContributor
3 years ago

When I comment out the .sdc in the .qip, this is better, I do not get the duplicated clock points.

Side effect is that there is one point in each PLL that has no clock definition:

Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|pmu_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|pmu_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|free_running_48mhz_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|free_running_48mhz_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Info(13166): Latch stratix10_fpga_a_mix_inst|PMU_TOP|flash_48M_clk_enable is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~c0cntr_reg 
Warning(332060): Node: stratix10_fpga_a_mix_inst|PMU_TOP|pmu_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg was determined to be a clock but was found without an associated clock assignment. 
	Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|pmu_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|pmu_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Warning(332060): Node: stratix10_fpga_a_mix_inst|PMU_TOP|free_running_48mhz_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg was determined to be a clock but was found without an associated clock assignment. 
	Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|free_running_48mhz_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|free_running_48mhz_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Warning(332060): Node: stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg was determined to be a clock but was found without an associated clock assignment. 
	Info(13166): Register stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~pll_e_reg__nff is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~ncntr_reg 
Warning(332060): Node: stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~c0cntr_reg was determined to be a clock but was found without an associated clock assignment. 
	Info(13166): Latch stratix10_fpga_a_mix_inst|PMU_TOP|flash_48M_clk_enable is being clocked by stratix10_fpga_a_mix_inst|PMU_TOP|flash_pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll~c0cntr_reg

(s10_iopll.fourteennm_pll~c0cntr_reg)