# Invalid time string specified: in ModelSim

My code is the following:

entity ex_or is
 port(a,b,c,d : in bit;
		x,y,z : out bit);
end ex_or;
architecture a of ex_or is
begin
	x <= a xor b;
	y <= a xor b xor c xor d;
	z <= (a and b) xor (c and d);
end a;

It is just an exercise from a Digital Electronic book, from the chapter of XOR gates. I'm just trying to get used with VHDL.

I already simulated an equally simple code to test AND and OR gates and it worked yesterday. But when I try to do it now, I get the same result.

I will take a look in this example, it seems useful. Thanks.

---

Edit: I just tried the example and got the same thing: Invalid time string specified, grey wave window. It doesn't seem to be something with code, but in some configuration or command.