Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- # Invalid time string specified --- Quote End --- If you are simulating Verilog, then try adding '-t ps' to the vsim command line to set the timescale to 1ps. You might also want to add something like `timescale 1 ps / 1 ps to your Verilog. --- Quote Start --- What does ModelSim offer that Quartus couldn't handle? --- Quote End --- A programmable method of generating a testbench. Drawing stimulus waveforms works for only the simplest of testbenches. Cheers, Dave