New Contributormy project suddenly gave an error [[ # ** Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time 90 ns. ]] after i added the values on the first input (B)
But when at input B=0 the simulation is successful and there is no error.
Cam someone help to fix this problem please?
Regular ContributorHi,
This error indicates that your design is stuck in an infinite loop. From your screenshots, I can't tell what the verb symbol does but perhaps the code for this symbol uses loops which is wrongly initialised or programmed in a way that requires a certain input (in your case B=0).
Regards,
Nurina
New Contributoradded a photo explaining what "verb" block is and its truth table.
Regular ContributorThanks. Can you share the "Waveform.vfw.vt" file? This has the code that we can investigate and debug.
Thanks,
Nurina
New Contributorhere waveform and also full project
Regular ContributorHi,
I think you should have flip flops in your design. Many of your inputs depend on the outputs so this might be the cause of it.
Regards,
Nurina
New ContributorBut i have the same scheme in Quartus II 4.0 and simulation is alright.
Regular ContributorHi,
Did you have your project migrated from v4.0 to this? Maybe it got corrupted in the process, or the settings of the project doesn't work after migration. Try reinserting the verb symbol, I tried that and it successfully simulated.
Regards,
Nurina
New ContributorI tried reinserting the verb symbol , вut it the same error. Can you give your corrected project with successfull simulation please.
Regular ContributorI also swapped ports A[0] and A[1] in the verb.bdf, so that could be it. Successful simulation can be found in waveform7. Note that I changed the file path name to mine in the Simulation Settings.
Regards,
Nurina
New ContributorI'm used your file and error is still here(
What wrong with my program?
I need all combination so i make new wafeform.
Regular ContributorI still think you should have flip flops. Or convert your bdf design to verilog/vhdl and then only simulate them. Because before each simulation, Quartus converts your design into verilog/vhdl code and if Quartus creates an erroneous code it will be difficult to debug. Also, simulations on University VWF often doesn't show all the signals involved and it'd be difficult to pinpoint where the problem arise.
Best way to perform an RTL simulation is by having all your designs in verilog/vhdl and write your own testbench and perform and RTL simulation on ModelSim or any 3rd party EDA tool.
As mentioned above quartus converts your design into code before simulation. The verilog/vhdl code generated by quartus might be different from v4.0 as compared to your current quartus version (which I assumed is 20.1 lite)
This problem is difficult to debug with your method of simulation. Intel and Altera has always discouraged the usage of bdf files because of the flawed conversion to verilog/vhdl code.
Regards,
Nurina
New Contributorthat is, you say that without the use of a verilog, my project will not be able to be correctly modeled due to an error when switching from a waveform to a verilog?
Regular ContributorNot waveform to verilog, the error comes from converting bdf to verilog. This is what the simulator does. It converts your bdf design into code for it to create a testbench and then only performs simulation. Sometimes this conversion does not work the way you want them to.
Regards,
Nurina
New ContributorOK, thanks, can I refer to your answer as a specialist's answer in my diploma?
Regular ContributorSure thing. I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Regards,
Nurina
PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.
