# ** Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time 90 ns.

I still think you should have flip flops. Or convert your bdf design to verilog/vhdl and then only simulate them. Because before each simulation, Quartus converts your design into verilog/vhdl code and if Quartus creates an erroneous code it will be difficult to debug. Also, simulations on University VWF often doesn't show all the signals involved and it'd be difficult to pinpoint where the problem arise.

Best way to perform an RTL simulation is by having all your designs in verilog/vhdl and write your own testbench and perform and RTL simulation on ModelSim or any 3rd party EDA tool.

As mentioned above quartus converts your design into code before simulation. The verilog/vhdl code generated by quartus might be different from v4.0 as compared to your current quartus version (which I assumed is 20.1 lite)

This problem is difficult to debug with your method of simulation. Intel and Altera has always discouraged the usage of bdf files because of the flawed conversion to verilog/vhdl code.

Regards,

Nurina